library ieee;
use ieee.std_logic_1164.all;

entity selectBlock_tb is
end entity selectBlock_tb;

architecture TESTBENCH of selectBlock_tb is
	
	component selectBlock
		port (
			Din : in bit_vector(31 downto 0);
			S : in bit_vector(1 downto 0);
			Dout : out bit_vector(31 downto 0);
			Carry : out bit
		);
	end component;
	
	for all : selectBlock use entity work.selectBlock(STRUCTURAL);
	
	signal I, O : bit_vector(31 downto 0);
	signal S : bit_vector(1 downto 0);
	signal C : bit;
	
begin
	
	SLCT : selectBlock port map(I, S, O, C);
	I <= "01010101010101010101010101010101";
	S <= "00", "01" after 20 ns, "10" after 40 ns, "11" after 60 ns;

end architecture TESTBENCH;
